Packaging of an Integrated circuit is needed to protect the semiconductor chip/die/Integrated circuit from physical damage that may occur while connecting the chip to the application printed circuit board or during its usage by the customer. Several different packaging types exist in the market including, for example, lead frame packages, ball grid array packages, chip scale packages such as wafer level chip scale packages, and so on.
Among these, a wafer level chip scale package (WLCSP) has the smallest form factor; that is, the package size is the same as the die size, and good electrical, mechanical, and thermal characteristics. It also has a simpler stack up and the assembly processing cost is lower compared to some of the other packaging solutions.
FIG. 1 illustrates the stack-up of a traditional WLCSP. After inspection of the silicon from the wafer fabrication foundry, including silicon 10, aluminum pad 12, and passivation layer 14, a layer 16 of polymer1 is coated and patterned. This is followed by a metal seed layer sputtering having a uniform thickness over the entire chip. This is then followed by the RDL metal plating 18. The thickness of this metal is uniform over the entire chip. Then a layer 20 of polymer2 is processed on the top of RDL. An under ball metal (UBM) layer 22 is first sputtered and then plated. The thickness of this UBM is uniform over the entire chip. This is followed by solder ball 24 placement.
There are several disadvantages of current practice. Most of the assembly suppliers allow a RDL to RDL spacing of at least 10 μm. In the future, as assembly processes advance, it is expected that assembly suppliers will support even <5 μm RDL-RDL spacing. With such low spacing, the chances of having cross-talk between RDL traces will increase. That is, a signal from one trace may be inadvertantly transmitted to the next trace.
Another disadvantage is that the layers between the conducting parts (UBM, RDL) can deteriorate over time because of dirt (pollution), moisture along the surface, humidity, etc. and can thus allow small amounts of current to flow across them, resulting in leakage currents. This phenomenon is also called tracking. If one RDL signal carries a low voltage signal and the neighboring one carries a high voltage signal, then in such cases, deterioration of the polymer can result in electrical shorts or device malfunctioning.
Furthermore, voltage levels on the RDL traces can be one reason for Copper-migration. If the potential difference between the RDL traces is higher, there is a high chance of formation of a conductive path between RDL traces over time; such phenomenon is called copper migration. Copper migration might result in electrical shorts or device malfunctioning.
The usual thickness of the RDL supported by assembly suppliers is at a minimum 4 μm. With such thickness there are chances of wafer warping during the assembly processing. This is the reason why most of the assembly suppliers limit the RDL density to a maximum of 75% for a unit package. This means 25% of the chip is RDL (copper) free, which results in an increase in thermal resistance or a reduced thermal performance.
U.S. Patent Applications 2017/0170122 (Ritter et al) and 2016/0148882 (Kim et al) teach methods of avoiding cross-talk in a WLCSP.